Intel Introduces New Way to Stack Chips on Top of Each Other

Dec. 14, 2018
Intel Introduces New Way to Stack Chips on Top of Each Other

Intel’s manufacturing lead has vanished over the last year as rivals Taiwan Semiconductor Manufacturing Corporation and Samsung have introduced the ability to build chips based on 7-nanometers. Intel has fallen behind with its 10-nanometer process, giving rivals like Qualcomm and AMD that outsource production a golden opportunity to loosen its hold over the personal computer and data center market.

But Intel is attempting to retake the lead with smarter—not smaller—manufacturing. The Silicon Valley company said it has started stacking computer chips in three dimensions and bonding them together in an attempt to simplify the development of custom chips. The 3D stacking technology, Foveros, gives Intel the ability not only to improve energy efficiency and speed but also respond faster to customer demands.

The $62-billion company, which was founded five decades ago, said that it would start constructing chips out of smaller units of silicon, more commonly called chiplets. Each device has a specific function and the use of high-bandwidth interconnects lets them act as though they are all on the same die. The Foveros technology should allow Intel to offer new combinations of memory and logic in the same device.

Intel says that no other company has been able to extend die stacking to high-performance logic, including CPU, GPU and AI cores. Intel says the first product based on the Foveros architecture will be available the second half of 2019. The chip will combine 10-nanometer logic on top of another 22-nanometer die featuring memory, power and I/O circuits. The layers will be connected with through-silicon vias (TSVs).

“Intel wants to use the best process for the targeted IP block, decoupled from a monolithic design’s solitary process and geometry,” said Patrick Moorhead, principal analyst at market researcher Moor Insights and Strategy. “Think of having a chip with the highest performance logic on one process, I/O on another, memories on another and analog on another, stitched together in a 3D package.”

Intel’s 3D technology follows the development of its 2.5D technology. The embedded multi-die interconnect bridge, or EMIB, gives Intel the ability to combine tiny interlocking slabs of silicon in two-dimensions. Small snippets of silicon are embedded in the underlying substrate to connect the chiplets. Intel says that the EMIB technology is lower cost than rival silicon interposer technologies, including TSMC’s CoWoS.

Advanced packaging technologies aim to make chip development more like circuit board design. The EMIB technology is currently used inside Intel’s Stratix 10 product line to connect the programmable FPGA, Xeon CPU and high bandwidth DRAM. Intel has also taken advantage of EMIB in another chip targeting personal computers, combining Intel’s Core CPU and AMD’s Radeon GPU with high bandwidth memory.

Intel’s EMIB technology is also aimed at lowering development costs, which have soared to hundreds of millions of dollars, according to industry analysts. The latest estimates are that it costs around $400 million to construct a single chip based on the 7-nanometer node. But since chiplets are smaller than monolithic die, companies can punch more chips out of every silicon wafer, potentially improving margins.

Other semiconductor firms are using modular chip development to curb costs. Using its Mochi architecture, Marvell Semiconductor has broadened the range of I/O available in its Armada server processors. Last month, Yaniv Kopelman, chief technology officer of Marvell’s networking unit, said that it planned to shift some networking products to the Mochi architecture, which was introduced in 2015.

Last month, AMD announced that its latest server processor will use cores based on the 7-nanometer process node surrounded by I/O based on 14-nanometer technology. That results in much higher performance cores at the same power and lower cost than traditional chips, said Mark Papermaster, the company’s chief technology officer. The parts communicate using AMD’s Infinity Fabric interconnect.

The Defense Advanced Research Projects Agency’s $1.5 billion Electronics Resurgence Initiative is also trying to jumpstart the development of standards that allow tiny silicon building blocks from different companies to work together. As part of the DARPA CHIPS program, Intel started giving anyone the ability to use the die-to-die interconnect behind EMIB, the advanced interface bus, or AIB.

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