Department of Defense Enlists Intel to Fab Future Leading-Edge Chips

Sept. 16, 2021
The decline of U.S. semiconductor fabs is leaving the Department of Defense with limited onshore access to leading-edge foundry technology that can meet the nation's long-term chip needs. Intel is stepping in to try to solve the problem.

Intel said it won a contract to supply leading-edge chip foundry services to the U.S. Department of Defense.

The contract was awarded last week as phase one of the DoD's Rapid Assured Microelectronics Prototypes Commercial program, or RAMP-C for short. Under the RAMP-C program, the agency is trying to guarantee it can use foundries located within the U.S. to get chips for aerospace and defense made on a state-of-the-art manufacturing node. It is partnering with Intel and other vendors to build the necessary foundry ecosystem.

"One of the most profound lessons of the past year is the strategic importance of semiconductors and the value to the United States of having a strong domestic semiconductor industry," said Intel CEO Pat Gelsinger. "Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge."

The U.S. accounts for only about 12% of global chip manufacturing capacity, as other nations have offered rich subsidies to encourage companies to build fabs. Furthermore, Intel has surrendered its ability to create the world's most advanced logic chips to rival TSMC, while Globalfoundries, the leading made-to-order chip foundry in the U.S., has halted the development of its most advanced nodes in favor of specialty processes.

Intel said the decline of semiconductor fabs in the U.S. is leaving the Department of Defense with limited onshore access to foundry technologies that can meet the nation's long-term needs for semiconductors.

The RAMP-C program will be led by Intel’s new foundry division, which it recently formed as part of a plan to regain its semiconductor crown by 2025. Intel said early in the year that it would build out a new business to make chips not only for its needs but also for other vendors (and even rivals) based on their blueprints. Intel Foundry Services is headed by Randhir Thakur, who previously ran Intel’s sprawling supply-chain operations.

Intel said it is partnering with several other companies on the program, including Cadence and Synopsys, the world's largest electronic design automation (EDA) software makers. IBM is also taking part in the project. While it has not manufactured chips for years, IBM invests in research that helps shapes the semiconductor industry. In May, it announced that it designed the world's first 2-nm test chip using "nanosheet" transistors.

The deal with the Department of Defense looks far into the future. Intel said it would work with its partners to establish an ecosystem to design and test chips based on the Intel "10A" manufacturing node–the most advanced process on its roadmap–due for production in 2025.

Intel said the 10A node takes advantage of innovations it plans to roll out in the 20A node in 2024. One area of improvement is in the structure of the transistors themselves, Intel's first overhaul in more than a decade.

For years, Intel, TSMC and other semiconductor giants have rolled out chips with transistors called FinFETs formed by placing fin-shaped protrusions between the source and drain sides of the channel. Transistors act as tiny electronic switches. The region that determines whether the switch is turned off or on—the gate—is draped over the fin, surrounding it on three sides and reducing the amount of power leaking from the device. These 3D transistors waste less power and, thus, operate faster and more efficiently than planar transistors.

Intel plans to move to a so-called gate-all-around transistor design called the RibbonFET starting in 2024. Instead of the fin partly covering the transistor, the fin is flipped on its side, so the gate surrounds a ribbon-shaped channel on all four sides, preventing even more power from leaking out. Intel said the RibbonFETs allow it to increase switching speeds at the same drive current as multiple fins in a smaller overall footprint.

Another feature Intel is bringing into the fold is its “backside power delivery system" called PowerVia. Today, the most advanced logic chips contain billions of transistors. Each one is covered by floors of interconnects that supply power to the transistor and send signals to other transistors on the chip, resembling stairwells in a miniature tower. The interconnects are formed by carving canals in the silicon and filling them with copper.

The problem is that the wires used for routing signals and relaying power to the transistors are tangled together, adding resistance that saps power efficiency. With PowerVia technology, Intel can instead bury the power rails behind the transistor instead of the front of the wafer. As a result, power can be delivered directly to the transistor above rather than traveling the long way through floors and floors of intertwined wires.

By placing the power rails on the underbelly of the transistor, PowerVia reduces resistance in the power delivery system. That results in less voltage dropoff from the power source to the transistors, allowing the chips to run cooler and more efficiently.

PowerVia also allows the wires on the front side of the wafer to be used exclusively for signal routing, improving frequencies.

Intel also plans to leverage a new manufacturing technology called High NA EUV in the 10A node. As part of its new process roadmap, Intel is expanding the use of EUV–short for extreme-ultraviolet lithography–tools, which use ultra-short wavelengths of light to scorch smaller transistors on polished slabs of silicon. These systems work in a way that reduces the risk of imperfections that can ruin the final chips, improving yields.

But it is also trying to get ahead of rivals using a more advanced technology called high numerical-aperture (High-NA) EUV, which uses more concentrated beams of light to sear smaller transistor patterns on wafers.

Intel plans to buy the first on the market through its partnership with semiconductor gear maker ASML.

Intel has also lured other players in the semiconductor industry to use its foundry services. Qualcomm has said it will collaborate with Intel to develop chips based on the 20A process node due in 2024. Amazon Web Services (AWS) plans to adopt advanced packaging tools Intel is opening up to clients through its foundry arm. Intel has previously said that it has had discussions with more than 100 potential foundry customers.

To grow its manufacturing footprint and give more "committed" capacity to foundry clients, Intel previously announced plans to spend $20 billion on two new fabs in Arizona as well as billions more at other locations.

“Along with our customers and ecosystem partners, including IBM, Cadence, Synopsys and others, we will help bolster the domestic semiconductor supply chain and ensure the United States maintains leadership in both R&D and advanced manufacturing," said Thakur, who leads Intel Foundry Services. "We look forward to a long-term collaboration with the U.S. government."

Intel did not share the dollar amount of the contract.

This article appeared in Electronic Design.

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